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WILSONVILLE, Ore.--(BUSINESS WIRE)--May 9, 2001-- Mentor Graphics Corp. (Nasdaq:MENT) today introduced FPGA Advantage 5.0, an enhanced version of the popular HDL flow that provides designers with an integrated solution and more robust functionality for design entry, management, simulation and synthesis of FPGAs.

Delivering across-the-board enhancements, FPGA Advantage 5.0 further simplifies the development of multi-million gate FPGAs by offering improved intellectual property (IP) support, new incremental synthesis technology and substantial improvements in Verilog and VHDL simulation performance.

``By offering tightly integrated design management, simulation and synthesis technology in one stand-alone solution, our designers have access to an easy-to-use and comprehensive FPGA and ASIC solution,'' said Ed Bochenski, design engineer, Sandia National Lab. ``FPGA Advantage increases our ability to meet time-to-product demands and develop truly next-generation FPGAs. With the introduction of FPGA Advantage 5.0, Mentor Graphics continues to raise the standard for designing FPGAs.''

Simplifying the Design Entry Process

At the design entry level, FPGA Advantage offers designers unequaled flexibility to create, manage, analyze and document HDL designs. FPGA designers now have the option to select from three design versions, including pure HDL source code (text-based support), graphical representations or both. In addition, the easy-to-use interface is ideal for multiple-site design teams working in Verilog, VHDL and mixed language designs. The enhanced design management capabilities offer a smoother integration of legacy code and commercial IP cores.

``As FPGAs continue to multiply in size, design management becomes an increasingly important element in the design process,'' said Valerie Rachko, director of marketing for FPGA Advantage. ``FPGA Advantage 5.0 provides a structured approach to complex programmable logic design that supports user preferences within a team-based environment, fostering collaborative design innovation.''

Enhanced RTL and Gate-Level Simulation

In the simulation process, designers will notice a dramatic improvement in the RTL and gate-level simulation of FPGAs. FPGA Advantage 5.0 has enhanced its Verilog gate-level simulation by 2-4X and VHDL and Verilog RTL simulation by as much as 2X. The design flow also offers a quickened debugging process and new features for monitoring any signal in the FPGA design, regardless of its location in the VHDL and mixed-language hierarchy.

Incremental Synthesis and FPGA Vendor Support

FPGA Advantage 5.0 has several enhanced synthesis features for the development of high-end FPGAs. In addition to improved run-times in algorithms and push-button methodology, FPGA Advantage 5.0 offers physical synthesis for identifying and reoptimizing critical paths in the design. By using post-place-and-route timing data, designers no longer need to reoptimize the entire design when an error in a path is detected, thus greatly improving time-to-market results.

FPGA Advantage 5.0 has also strengthened its FPGA vendor support. Xilinx CORE Generator(TM) and Altera MegaWizard® interfaces have been incorporated into the design process, providing designers with a seamless integration between FPGA Advantage 5.0 and vendor IP. The vendor cores slide directly into the FPGA Advantage environment, speeding up the design construction and facilitating management of the design area.

Pricing and Availability

FPGA Advantage 5.0 is available immediately through Mentor Graphics' unique multi-tiered distribution network. All versions of FPGA Advantage 5.0 support all major FPGA vendors. Customers have the ability to choose from an entry-level FPGA design flow solution designed for the single FPGA designer, starting at $12,000 to a complex FPGA design flow solution with an ASIC option for workgroups starting at $45,000. Additional information on FPGA Advantage 5.0 can be found on the World Wide Web at www.fpga-advantage.com.

About Mentor Graphics Corp.

Mentor Graphics Corp. (Nasdaq:MENT) is a world leader in electronic hardware and software design solutions, providing products and consulting services for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of nearly $600 million and employs approximately 2,750 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Ore. 97070-7777; Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, Calif. 95131-2314. World Wide Web site: www.mentor.com.

Mentor Graphics and FPGA Advantage are registered trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.

     Mentor Graphics
     Rebecca Granquist, 503/685-7000
     rebecca_granquist@mentor.com
     or
     Benjamin Group/BSMG Worldwide
     Jason Khoury, 415/352-2628 ext. 635
     jason@benjamingroup.com